Hermetically-sealed electrical circuit apparatus

ABSTRACT

Hermetically-sealed electrical circuit apparatus and methods for constructing such apparatus using one or more seal portions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Ser.No. 61/185,881 filed 10 Jun. 2009, entitled “FARADAY CAGE FOR CIRCUITRYUSING SUBSTRATES,” U.S. Provisional Application Ser. No. 61/229,867filed 30 Jul. 2009, entitled “APPARATUS FOR RESTRICTING MOISTUREINGRESS,” U.S. Provisional Application Ser. No. 61/229,869 filed 30 Jul.2009, entitled “HERMETICITY TESTING,” and U.S. Provisional ApplicationSer. No. 61/235,745 filed 21 Aug. 2009, entitled “HERMETICALLY-SEALEDELECTRICAL CIRCUIT APPARATUS,” all of which are incorporated herein byreference in their respective entireties.

BACKGROUND

The disclosure herein relates to hermetically-sealed electrical circuitapparatus, and further to fabrication methods for constructing suchapparatus.

Electrical circuits (e.g., integrated circuits) include many types ofactive and passive devices (e.g., transistors, capacitors, resistors,etc.) that may be subject to damage from moisture (e.g., corrosion andfunctional changes to the system). For example, moisture may affect theoperation and performance of circuitry, such as sensitive circuits usedin implantable medical devices (e.g., sensor circuitry, pacingcircuitry, timing circuitry, etc.).

Various attempts have previously been made to seal the interior ofsemiconductor device dies from moisture ingress. The bottom substrate inmany semiconductor devices (e.g., silicon) effectively blocks moisturefrom entering the interior of the die from the bottom, but materialscommonly employed in fabricating further layers above the substrateprovide a path for moisture to enter from the top and/or sides of thedie, e.g., after die separation. For example, certain commonly employedinsulator materials such as silicon dioxide (SiO₂) may be penetrated bymoisture.

SUMMARY

The disclosure herein relates generally to hermetically-sealedelectrical circuit apparatus, and methods of fabrication of suchapparatus. For example, as described in one or more embodiments herein,semiconductor substrates and semiconductor fabrication techniques may beused to provide a hermetic enclosure around a circuit device (e.g., adie that includes circuitry).

One exemplary apparatus disclosed herein includes an electrical circuitapparatus. The electrical circuit apparatus includes a first portion, asecond portion, at least one circuit, and one or more seal portions. Thefirst portion includes a planar connection surface, a substrate providedfrom a wafer (e.g., the substrate includes a substrate surface oppositethe planar connection surface) and at least one side surface extendingbetween the substrate surface and the planar connection surface. Thesecond portion includes a planar connection surface, a substrateprovided from a wafer (e.g., the substrate comprises a substrate surfaceopposite the planar connection surface), and at least one side surfaceextending between the substrate surface and the planar connectionsurface. The planar connection surface of the first portion is bonded tothe planar connection surface of the second portion to form an interfacedefining at least one interface edge about the perimeter of theinterface between the planar connection surfaces of the first portionand the second portion. The at least one circuit device includeselectrical circuitry. Further, the at least one circuit device isencompassed by at least portions of the first portion and the secondportion. The one or more seal portions cover at least the at least oneinterface edge of the interface to restrict moisture from ingressinginto the apparatus.

One exemplary method disclosed herein includes providing at least oneelectrical circuit apparatus. The method includes providing a firstportion, providing a second portion, and providing at least one circuitdevice comprising electrical circuitry. The first portion includes aplanar connection surface, a substrate provided from a wafer (e.g., thesubstrate comprises a substrate surface opposite the planar connectionsurface), and at least one side surface extending between the substratesurface and the planar connection surface. The second portion includes aplanar connection surface, a substrate provided from a wafer (e.g., thesubstrate comprises a substrate surface opposite the planar connectionsurface), and at least one side surface extending between the substratesurface and the planar connection surface. The method further includescoupling the planar connection surface of the first portion to theplanar connection surface of the second portion to form an interfacedefining at least one interface edge about the perimeter of theinterface between the planar connection surfaces of the first portionand the second portion. After such coupling, the at least one circuitdevice is encompassed by at least portions of the first portion and thesecond portion. The method further includes providing one or more sealportions covering at least the at least one interface edge of theinterface to restrict moisture from ingressing into the apparatus.

The above summary is not intended to describe each embodiment or everyimplementation of the present disclosure. A more complete understandingwill become apparent and appreciated by referring to the followingdetailed description and claims taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C are illustrative cross-sectional side views generallydepicting a method for fabricating one exemplary embodiment of ahermetically-sealed electrical circuit apparatus.

FIG. 2A is an illustrative cross-sectional view of one exemplaryembodiment of an electrical circuit apparatus such as generally shown inFIGS. 1A-1C.

FIG. 2B is an illustrative cross-sectional view of another exemplaryembodiment of an electrical circuit apparatus such as generally shown inFIGS. 1A-1C.

FIG. 2C is an illustrative cross-sectional view of still anotherexemplary embodiment of an electrical circuit apparatus such asgenerally shown in FIGS. 1A-1C.

FIG. 2D is an illustrative cross-sectional view of yet still anotherexemplary embodiment of an electrical circuit apparatus such asgenerally shown in FIGS. 1A-1C.

FIG. 3A is an illustrative cross-sectional view of one exemplaryembodiment of an electrical circuit apparatus, such as generally shownin FIGS. 1A-1C, including first and second portions having differentsizes.

FIG. 3B is an illustrative cross-sectional view of another exemplaryembodiment of an electrical circuit apparatus, such as generally shownin FIGS. 1A-1C, including first and second portions having differentsizes.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

In the following detailed description of illustrative embodiments,reference is made to the accompanying figures of the thawing which forma part hereof, and in which are shown, by way of illustration, specificembodiments which may be practiced. It is to be understood that otherembodiments may be utilized and structural changes may be made withoutdeparting from (e.g., still falling within) the scope of the disclosurepresented hereby.

Exemplary apparatus, and methods of constructing such apparatus, shallbe described with reference to FIGS. 1-3. It will be apparent to oneskilled in the art that elements from one embodiment may be used incombination with elements of the other embodiments, and that thepossible embodiments of such apparatus using combinations of featuresset forth herein is not limited to the specific embodiments shown in theFigures and/or described herein. Further, it will be recognized that theembodiments described herein may include many elements that are notnecessarily shown to scale. Still further, it will be recognized thatthe size and shape of various elements herein may be modified but stillfall within the scope of the present disclosure, although one or moreshapes and/or sizes, or types of elements, may be advantageous overothers.

FIGS. 1A-1C show illustrative cross-sectional views generally depictinga method for fabricating one exemplary embodiment of ahermetically-sealed electrical circuit apparatus 10 (see FIG. 1C)including at least one circuit device 90. The method may includeproviding a first portion 20 and a second portion 40.

Wafer scale fabrication techniques may be used to provide each of thefirst and second portions 20, 40. In one or more embodiments, each ofthe first portion 20 and the second portion 40 includes a substrate 22,42, respectively, provided from or as a part of a wafer (e.g., a portionof any size and shape of substrate usable in wafer scale fabricationprocesses, such as a circular silicon wafer, a glass substrate, aplastic substrate, etc.). In other words, multiple portions may befabricated on a wafer (e.g., the first portions on a first wafer and thesecond portions on a second wafer). As such, the fabrication of each ofthe portions may be initiated with use of a wafer substrate (e.g., asemiconductor, conductor, or insulator substrate wafer). In one or moreembodiments, the wafer substrate is a doped semiconductor wafersubstrate (e.g., doped to either a bulk n-type or p-type wafer), such asthose used as the base substrate for microelectronic devices (e.g.,substrates built in and over using one or more microfabrication processsteps such as doping, ion implantation, etching, deposition of variousmaterials, and photolithographic patterning processes). In one or moreembodiments, the wafer is a silicon wafer. However, other availabletypes of semiconductor wafers may be used, such as, for example, agallium arsenide wafer, a germanium wafer, a silicon on insulator (SOI)wafer, etc. Further, for example, in one or more embodiments, thesubstrate may be formed of one or more materials other thansemiconductor material, such as a glass substrate, wherein the substrateincludes a metal film. In other words, for example, the first portion 20may include a substrate 22 provided from or as a part of a wafer and thesecond portion 40 may include a substrate 42 provided from or as a partof a wafer.

As shown in FIGS. 1A-1C, the substrate 22 may include a substratesurface 23 located opposite a connection surface 25 of the first portion20. The first portion 20 further includes one or more layers 24 formedon the substrate 22 terminating at the connection surface 25 (e.g., aplanar connection surface, a connection surface orthogonal to the atleast one side surface 21, etc.). Also, the first portion 20 includes atleast one side surface 21 (e.g., one side surface, four side surfaces,etc.) extending between the substrate surface 23 and the connectionsurface 25 (e.g., defined by the substrate 22 and the one or more layers24).

At least in one embodiment, the second portion 40 may only include asubstrate (e.g., substrate 42). In the embodiment depicted, the secondportion 40 is substantially similar to the first portion 20. Forexample, the substrate 42 may include a substrate surface 43 locatedopposite a connection surface 45 of the second portion 40. The secondportion 40 may further include one or more layers 44 formed on thesubstrate 42 terminating at the connection surface 45 (e.g., a planarconnection surface, a connection surface orthogonal to the at least oneside surface 41). Also, the second portion 40 may include at least oneside surface 41 (e.g., one side surface, four side surfaces, etc.)extending between the substrate surface 43 and the connection surface 45(e.g., defined by the substrate 42 and the one or more layers 44).

At least in one embodiment, the connection surfaces 25, 45, which may bedefined at least partly by one or more layers; may include oxidematerial. For example, such oxide material may be oxide material formed,deposited or grown as part of one or more processing steps (e.g., oxidessuch as borophosphosilicate glass, silicon dioxide, native oxide, etc.).

The apparatus 10 may include one or more circuit devices 90 (e.g., atleast one circuit device 90) encompassed by (e.g., within, surroundedby, etc.) at least portions of the first and the second portions 20, 40.In at least one embodiment (as shown in FIGS. 1A-1C), the first portion20 and/or the second portion 40 may be processed to form one or morecircuit devices 90 by fabricating (e.g., using any known fabricationprocesses including deposition, patterning, and/or etching) the one ormore circuit device 90 within the one or more layers 24, 44 fowled onthe substrates 22, 42. In other words, the one or more circuit devices90 may be formed as part of the one or more layers 24, 44 of the firstand second portions 20, 40, respectively.

The first and second portions 20, 40 may further include one or morecontact pads 30, 50, respectively, electrically coupled to the one ormore circuit devices 90 using one or more interconnects 32, 52(represented schematically with dashed lines) and located at theconnection surfaces 25, 45. When the first portion 20 is assembled(e.g., bonded) with the second portion 40, the contact pads 30, 50 areelectrically coupled to each other such that the one or more circuitdevices 90 are electrically coupled to each other. Further, although notdepicted, the apparatus 10 (e.g., the first portion 20 and/or the secondportion 40) may include one or more additional interconnects extendingbetween the circuit devices 90 and any other surface (e.g., outsidesurface) or any other location of the apparatus 10 for any purpose.

Further, although not depicted, one or both of the first and secondportions 20, 40 (e.g., the one or more layers 24, 44) may define acavity and at least one of the one or more circuit devices 90 may belocated within the cavity. As used herein, the one or more circuitdevices 90 may be any device or devices that include electricalcircuitry that performs one or more functions (e.g., die containingcircuitry). In such embodiments, the one or more circuit devices 90 maybe directly electrically coupled to the one or more contacts pads 30, 50without the use of interconnects (e.g., interconnects 32, 52). Forexample, at least in one embodiment, the second portion 40 defines acavity extending into the connection surface 45. A circuit device 90 maybe located within the cavity and electrically coupled to the contactpads 30 of the first portion 20.

The one or more circuit devices 90, the one or more interconnects 32,52, and the one or more contact pads 30, 50 may be formed using standardmicroelectronic fabrication processing techniques (e.g., such as etchingof materials, deposition of materials, and photolithographic patterningprocess steps, etc.). Further, various portions of first and secondportions 20, 40 may be formed during the same or different processingsteps. The present disclosure is not limited to any particularprocessing, or timing or order, of such process steps. However, sometypes of processing and order thereof may be beneficial over othertypes.

The method further includes bonding (e.g., oxide bonding,plasma-enhanced direct wafer bonding, etc.) the first portion 20 to thesecond portion 40 to form an interface 12 defining at least oneinterface edge 14 about the perimeter of the interface 12 (e.g., theinterface 12 between the planar connection surfaces 25, 45 of the firstand the second portions 20, 40) (see FIG. 1B). The interface 12 betweenthe connection surfaces 25, 45, of the first portion 20 and the secondportion 40 may be hermetic. As used herein, an interface that ishermetic is an interface that restricts (e.g., substantially limits,slows, prevents, etc.) moisture from passing, diffusing, pervading,infiltrating, and/or leaking through itself (e.g., the interface 12 mayrestrict moisture from passing, diffusing, pervading, infiltrating,and/or leaking through itself). As used herein, “moisture” may bedefined as any material capable of ingressing into semiconductordevices. For example, moisture may include water, biological liquids,vapors, gases, etc.

In one or more embodiments, bonding the first and second portions 20, 40together to assemble the apparatus 10 may be implemented using any waferor die bonding process (e.g., bonding a wafer including the firstportions with a wafer including the second portions, which also refersto the bonding of an individual die to a full wafer, an individual dieto another individual die, etc.), such as chemical bonding processes(e.g., those using adhesion promoters, high temperature bondingprocesses, hydrogen bonding processes, plasma-enhanced bondingprocesses, oxide bonding processes, etc.). For example, use ofplasma-enhanced bonding permits oxide surfaces (e.g., portions of theconnection surfaces 25, 45 of the first and second portions 20, 40including a dioxide material, such as silicon oxide or native oxide) tobe bonded together.

Further, for example, in one or more embodiments, the connectionsurfaces 25, 45 may be each etched, polished, or planarized (e.g., usinga chemical mechanical planarization or polishing) to expose anyconductive portions thereof (e.g., the contact pads 30, 50 at connectionsurfaces 25, 45) to be exposed. For example, when the oxide portions andthe conductive portions (e.g., contact pads 30) located at theconnection surface 25 (e.g., a planar surface) are aligned with theoxide portions and the conductive portions (e.g., contact pads 50)located at the connection surface 45 (e.g., a planar surface),plasma-enhanced bonding may be performed. Further, plasma-enhancedbonding processes may form a bond between oxide portions of theconnection surfaces 25, 45 of the first and second portions 20, 40without the need for adhesives or other intermediate layers. Forexample, at least in one embodiment, the bonding at the interface 12 maybe formed by driving off any existing water present between theconnection surfaces 25, 45 and forming silicon-oxygen bonds throughoutthe structure such that a covalent bond is formed.

The method further includes providing one or more seal portions 60 atleast covering the at least one interface edge 14 that, e.g., restrictsmoisture from entering the interface between the connection surfaces 25,45 (e.g., planar connection surfaces) of the first and second portions20, 40, respectively. As shown in FIG. 1C, the one or more seal portions60 include a layer covering the entire exterior surface (e.g., thesubstrates surfaces 23, 43, the at least one side surfaces 41, 21, theinterface 14, etc.). In at least one embodiment, the one or more sealsportions 60 only cover a portion of the exterior surface of theapparatus 10 (e.g., one or more portions of one or both of the at leastone side surface 21, 41 defined by either or both of the one or morelayers 24, 44 of the first and the second portions 20, 40; one or moreportions of one or both of the at least one side surface 21, 41 definedby either or both of the substrates 22, 42 of the first and the secondportions 20, 40; one or more portions of the substrate surfaces 23, 43of the first and the second portions 20, 40; etc.).

The one or more seal portions 60 may be provided by forming ordepositing (e.g., physical deposition, chemical deposition, etc.) theone or more seal portions 60 as part of one or more processing steps(e.g., masking and depositing). For example, in at least one embodiment,the one or more seal portions 60 are provided by sputtering metals orpolysilicon. Further, for example, in at least one embodiment, the oneor more seal portions 60 are provided by chemical-vapor deposition.

The one or more seal portions 60 may include various materials such as,e.g., oxide materials, semiconductor materials, conductor materials,insulator materials, polysilicon, metals, phosphosilicate glass,borophosphosilicate glass, silicon nitride, tetraethyl orthosilicate,silox, etc. Further, such material of the one or more seal portions 60may be biocompatible (e.g., such as for use in implantable medicaldevices). The one or more seal portions 60 may have a thickness of about1 angstrom. Further, the one or more seal portions 60 may have athickness of about 1 angstrom or more (in other words, at least about 1angstrom), about 2 angstroms or more, about 5 angstroms or more, about10 angstroms or more, about 50 angstroms or less, about 25 angstroms orless, about 10 angstroms or less, about 7 angstroms or less, about 5angstroms or less, about 2 angstroms or less, or about 1 angstroms orless, etc. In at least one embodiment, the one or more seal portions 60have a thickness that is thicker than the thickness of any material thatmay naturally form or grow on the first and second portions 20, 40(e.g., native oxide).

In at least one embodiment, the one or more seal portions 60 may includeone or more layers of the same or various materials formed in the sameor different process. Further, each layer of the one or more layersforming the one or more seal portions 60 may have a thickness of atleast about 1 angstrom. For example, the one or more seal portions 60may include atomic layer deposition of dielectrics, sputtering ofmetals, chemical-vapor deposition of silicon nitride, etc

The apparatus 10 as shown in FIG. 1C may be utilized as a standalonepackage (e.g., apparatus 10 may not need any additional integratedcircuit packaging or encapsulation). In at least one embodiment,however, one or more barrier layers (not shown) may be provided (e.g.,formed) over the apparatus 10 after the one or more seal portions 60have formed thereon. For example, the apparatus 10 may be encapsulatedin silicone, medical adhesive, titanium, etc.

The process flow presented in FIGS. 1A-1C is only an exemplary methodthat may be used to implement the apparatus described herein and is notto be taken as limiting to the scope of the disclosure provided herein.Various modifications to the process and/or timing or order of theprocess steps may be made to the method while still providing thebenefits of apparatus described herein.

Although not limited thereto, in one or more embodiments, the apparatus10 is beneficial circuitry for packaging used in implantable medicaldevices. For example, the one or more circuit devices 90 of theapparatus 10 may be a part of an implantable medical device. Further,the apparatus 10 may be biocompatible. For example, the implantablemedical device may be a device implantable in a body near a human heart.For example, the implanted medical device may be any implantable cardiacpacemaker, defibrillator, cardioverter-defibrillator, orpacemaker-cardioverter-defibrillator (PCD). Further, for example, theimplantable medical device may be an implantable nerve stimulator ormuscle stimulator, an implantable monitoring device (e.g., a hemodynamicmonitoring device), a brain stimulator, a gastric stimulator, a drugpump, or any other implantable device that would benefit from moistureprotection. Therefore, the apparatus 10 may find wide application in anyform of implantable medical device. As such, any description hereinmaking reference to any particular medical device is not to be taken asa limitation of the type of medical device which can benefit from andwhich can employ apparatus 10 as described herein.

Further, although the apparatus 10 may be beneficial for implantablemedical devices, such structure is in no manner limited to suchapplications. For example, such testing structure may be beneficial formany different types of circuitry (e.g., whether for medical use or not,whether for an implantable medical device or not). For example, one ormore types of circuits that may benefit from such testing structure mayinclude circuits such as sensor circuits, pacing circuits, timingcircuits, telemetry circuits, etc.

FIGS. 2A-2D and 3A-3B are illustrative cross-sectional views ofexemplary embodiments of electrical circuit apparatus such as generallyshown in FIGS. 1A-1C. Each embodiment depicted in each of FIGS. 2A-2Dand 3A-3B utilizes many of the same components/portions, and as such,utilizes the same reference numbers in the description provided herein.However, each embodiment depicted in each of FIGS. 2A-2D and 3A-3B isconstructed in different configurations.

The electrical circuit apparatus 210 may be similar to the electricalcircuit apparatus 10 and components thereof described herein withreference to FIGS. 1A-1C. For example, electrical circuit apparatus 210includes a first portion 220 (e.g., including a substrate 222, asubstrate surface 223, one or more layers 224, a connection surface 225,at least one side surface 221, a circuit device 290, contact pads 230,and interconnects 232 (represented schematically with dashed lines)), asecond portion 240 (e.g., including a substrate 242, a substrate surface243, one or more layers 244, a connection surface 245, at least one sidesurface 241, a circuit device 290, contact pads 250, and interconnects252 (represented schematically with dashed lines)), an interface 212defining at least one interface edge 214 about the perimeter of theinterface 212, and a one or more seal portions 260. As such, forsimplicity, further description on some of the details of the electricalcircuit apparatus 210 shall not be provided.

The one or more seal portions 260 are located in various locations onthe exemplary electrical circuit apparatus 210 depicted in FIGS. 2A-2D.For example, the one or more seal portions 260 cover a portion of the atleast one side surface 221 of the first portion 220 and at least aportion of the at least one side surface 241 of the second portion 240of the electrical circuit apparatus 210 in FIG. 2A. More specifically,the at least one interface edge 214 and portions of the side surfaces221, 241 defined by portions of both of the one or more layers 224, 244are covered by the one or more seal portions 260 such that the one ormore seal portions 260 restrict moisture ingress (e.g., movement ofmoisture) into the electrical circuit device 290 (e.g., through theinterface 212), e.g., to protect the circuit devices 290. The one ormore seal portions 260 may extend around the entire interface edge 214or one or more portions of interface edge 214 (e.g., one or more sidesso as to restrict moisture ingress from particular directions).

Further, the apparatus 210 depicted in FIG. 2A includes interconnects232, 252 extending within the one or more layers 224, 244, respectively,between the circuit devices 290 and the contact pads 230, 250. Thecontact pads 230, 250 are located within the one or more layers 224, 244proximate the respective side surfaces 221, 241 without being covered bythe one or more seal portions 260 such that, e.g., they may electricallyconnected to any other device. Although only two contact pads 230, 250and two interconnects 232, 252 are depicted in FIG. 2A, the electricalcircuit apparatus 210 may include more or less than two contact pads andtwo interconnects electrically coupled to the circuit devices 290. As aresult of interconnects 232, 252 and contact pads 230, 250, the circuitdevices 290 may be in electrical communication with a device locatedoutside of the electrical circuit apparatus 210 by electrically couplingsuch device to the contact pads 230, 250. Further, the circuit devices290 of the first and second portions 220, 240 may be electricallycoupled to each other by the use of interconnects (not shown) similar tothe electrical circuit devices 90 depicted in FIGS. 1A-1C.

The formation of interconnects 232, 252 and the contact pads 230, 250may be formed using standard microelectronic fabrication processingtechniques (e.g., such as etching of materials, deposition of materials,photolithographic patterning process steps, etc.). Further,interconnects 232, 252 may be formed of various structures including,e.g., stacked vias, through-silicon vias, metal layers, etc. Variousportions of first and second portions 220, 240 may be formed during thesame or different processing steps. For example, a portion of aninterconnect 232 may be formed within a layer of the one or more layers224 during formation of device 290. Still further, for example, processsteps to form interconnects 232, 252 may be completely separatetherefrom, such as in the formation of a through-silicon via after otherlayer processing is completed. The present disclosure is not limited toany particular processing, or timing or order, of such process steps.However, some types of processing and order thereof may be beneficialover other types.

Still further, in one or more embodiments, the first and second portions220, 240 may not include interconnects or vias connecting the circuitdevices to contact pads on the outside of the apparatus 210. Forexample, in at least one embodiment, the apparatus 210 may includevarious apparatus and/or structures to wirelessly communicate to otherdevices/apparatus outside of apparatus 210.

One or more seal portions 260 cover a larger portion of the sidesurfaces 221, 241 of the electrical circuit apparatus 210 in FIG. 2Bthan in FIG. 2A. More specifically, the interface edge 214, portions ofside surfaces 221, 241 defined by the one or more layers 224, 244, and aportion of the substrates 222, 242 are covered by the one or more sealportions 260 such that one or more seal portions 260 restrict moistureingress (e.g., movement of moisture) into the electrical circuitapparatus 210 (e.g., through the interface 212, one or more layers 224,244, etc.), e.g., to protect the circuit devices 290.

The apparatus 210 depicted in FIG. 2B includes interconnects 232, 237,252 extending between the circuit devices 290 and the contact pads 230,250. In this embodiment, the contact pads 230, 250 are located proximatethe substrate surface 243 of the second portion 240. The interconnect232 extends through the one or more layers 224 of the first portion 220to a contact pad 234. The contact pad 234 is electrically coupled tocontact pad 236 when the first portion 220 is coupled to the secondportion 240. The contact pad 236 is electrically coupled to interconnect237, which extends through the second portion 240 (e.g., the one or morelayers 244 and the substrate 242) to the contact pad 230 therebyelectrically coupling the contact pad 230 and the circuit device 290 ofthe first portion 220. The interconnects described herein may also use asimilar connection (using contact pads, etc.) between the one or morelayers and substrate of a respective portion. Further, interconnect 252extends through the one or more layers 244 and the substrate 242 and iselectrically coupled to contact pad 250. Although only contact pads 230,250 and interconnects 232, 237, 252 are depicted in FIG. 2B, theelectrical circuit apparatus 210 may include more than two contact padsand/or more than three interconnects electrically coupled to the circuitdevices 290.

Further, for example, one or more seal portions 260 may cover thesubstrate surface 243 of the second portion 240 and a portion of theside surfaces 221, 241 of the electrical circuit apparatus 210 as shownin FIG. 2C. More specifically, the interface edge 214, the side surface221 defined by the substrate 242, the side surfaces 221, 241 defined bythe one or more layers 244, the side surface 221 defined by a portion ofthe substrate 222, and the substrate surface 243 are covered by the oneor more seal portion 260 such that one or more seal portions 260restrict moisture ingress (e.g., movement of moisture) into theelectrical circuit apparatus 210 (e.g., through the interface 212,through the one or more layers 224, 244, etc.) to, e.g., protect thecircuit devices 290.

The apparatus 210 depicted in FIG. 2C includes interconnects 232, 252extending between the circuit devices 290 and the contact pads 230, 250.In this embodiment, the contact pads 230, 250 are located proximate thesubstrate surface 223 of the first portion 220. The interconnect 252extends through the one or more layers 244 of the second portion 240 andthrough the one or more layers 224 and substrate 222 of the firstportion 220 to the contact pad 250 (e.g., electrically coupled to thecontact pad 250). Although not depicted in FIG. 2C, the interconnect 252may include multiple portions and/or contact pads (e.g., contact padslocated proximate each of the connection surfaces 225, 245 so as tocomplete the interconnect 252 when the first portion 220 is bonded tothe second portion 240 similar to contact pads 234, 236 shown in FIG.2B). Further, interconnect 232 extends through the one or more layers224 and the substrate 222 to contact pad 230 (e.g., electrically coupledto the contact pad 230). Although only contact pads 230, 250 andinterconnects 232, 252 are depicted in FIG. 2C, the electrical circuitapparatus 210 may include more than two contact pads and/or more thantwo interconnects electrically coupled to the circuit devices 290.

Still further, for example, one or more seal portions 260 may cover atleast a portion of the substrate surface 243 of the second portion 240and a portion of the side surfaces 221, 241 of the electrical circuitapparatus 210 as shown in FIG. 2D. More specifically, the interface edge214, the side surfaces 221, 241 defined by the one or more layers 224,244, the side surface 221 defined by least a portion of the substrate222, the surface 241 defined by the substrate 242, and at least aportion of the substrate surface 243 are covered such that one or moreseal portions 260 restrict moisture ingress (e.g., movement of moisture)into the electrical circuit apparatus 210 (e.g., through the interface212, through one or more layers 224, 244, etc.), e.g., to protect thecircuit devices 290.

The apparatus 210 depicted in FIG. 2D includes interconnects 232, 252extending between the circuit devices 290 and the contact pads 230, 250in a similar manner to that shown in FIG. 2C but to surface 243 insteadof to surface 223.

The apparatus 210 depicted in FIGS. 3A-3B includes first portions 220that are larger than the second portions 240 (e.g., the connectionsurface 225 of the first portion 220 defines a larger area than theconnection surface 245 of the second portion 240). In at least oneembodiment, the second portion 240 when bonded to the first portion 220is centered within the area defined by the connection surface 225 of thefirst portion 220. The first portion 220 and the second portion 240 maybe any size relative to each other so as to provide suitablefunctionality to the apparatus 210 (e.g., to provide contact pads onvarious locations of the apparatus 210 for electrically coupling theapparatus 210 to various devices, to reduce the size and/or shape of theapparatus 210, to reduce the amount of material used to form theapparatus 210, etc.).

The apparatus 210 depicted in FIGS. 3A-3B, however, differ from eachother in that at least the angle and/or shape of their respective sidesurfaces 241 of the second portions 240 differ. For example, the secondportion 240 depicted in FIG. 3A includes at least one side surface 241that is substantially perpendicular to the connection surface 245 suchthat the area of the substrate surface 243 is about equal to the area ofthe connection surface 245. The second portion 240 depicted in FIG. 3Bincludes at least one side surface 241 that is not perpendicular butrather is less than 90 degrees (e.g., the angle alpha between the atleast one side surface 241 and the connection surface 254 may be about89 degrees, 85 degrees, 80 degrees, 70 degrees, 60 degrees, 50 degrees,45 degrees, 40 degrees, 30 degrees, etc.) to the connection surface 245such that the area of the substrate surface 243 is smaller than the areaof the connection surface 245.

The one or more seal portions 260 are located in substantially the samelocations on the exemplary electrical circuit apparatus 210 depicted inFIGS. 3A-3B. For example, the one or more seal portions 260 cover the atleast one side surface 241 defined by the one or more layers 244 andsubstrate 242 of the second portion 240, at least a portion of thesubstrate surface 243 of the second portion 240, and at least a portionof the connection surface 225 of the first portion 220 of the electricalcircuit apparatus 210. Further, the at least one interface edge 214between the connection surface 225 of the first portion 220 and theconnection surface 245 of the second portion 240 is covered such thatthe one or more seal portions 260 restrict moisture ingress (e.g.,movement of moisture) into the electrical circuit device 290 (e.g.,through the interface 212, through the one or more layers 224, 244,etc.), e.g., to protect the circuit devices 290.

Further, the apparatus 210 depicted in FIGS. 3A-3B includesinterconnects 232, 252 extending between the circuit devices 290 and thecontact pads 230, 250. The contact pads 230, 250 are located proximatethe substrate surface 243 of the second portion and are not covered bythe one or more seal portions 260 such that, e.g., they may beelectrically connected to any other device. Interconnect 232 extendsthrough the one or more layers 224 of the first portion 220 and the oneor more layers 244 and substrate 242 of the second portion 240. Further,interconnect 252 extends through the one or more layers 244 andsubstrate 242 of the second portion 240. Although not depicted in FIGS.3A-3B, the interconnect 232 may include multiple portions and/or contactpads (e.g., contact pads located proximate each of the connectionsurfaces 225, 245 so as to complete the interconnect 232 when the firstportion 220 is bonded to the second portion 240 similar to contact pads234, 236 shown in FIG. 2B). Further, although only two contact pads 230,250 and two interconnects 232, 252 are depicted in FIGS. 3A-3B, theelectrical circuit apparatus 210 may include more than two contact padsand/or interconnects electrically coupled to the circuit devices 290. Asa result of these contact pads and interconnects, the circuit devices290 may be in electrical communication with a device located outside ofthe electrical circuit apparatus 210 by connecting such device to thecontact pads 230, 250. Further, the circuit devices 290 of the first andsecond portions 220, 240 may be electrically coupled to each other bythe use of interconnects (not shown) similar to the electrical circuitdevice 10 depicted in FIGS. 1A-1C.

Any features, components, and/or properties of any of the embodimentsdescribed herein may be incorporated into any other embodiment(s)described herein.

All patents, patent documents, and references cited herein areincorporated in their entirety as if each were incorporated separately.This disclosure has been provided with reference to illustrativeembodiments and is not meant to be construed in a limiting sense. Asdescribed previously, one skilled in the art will recognize that othervarious illustrative applications may use the techniques as describedherein to take advantage of the beneficial characteristics of theapparatus and methods described herein. Various modifications of theillustrative embodiments, as well as additional embodiments of thedisclosure, will be apparent upon reference to this description.

1. An electrical circuit apparatus comprising: a first portioncomprising: a planar connection surface, a substrate provided from awafer, wherein the substrate comprises a substrate surface opposite theplanar connection surface, and at least one side surface extendingbetween the substrate surface and the planar connection surface; asecond portion comprising: a planar connection surface, a substrateprovided from a wafer, wherein the substrate comprises a substratesurface opposite the planar connection surface, and at least one sidesurface extending between the substrate surface and the planarconnection surface, wherein the planar connection surface of the firstportion is bonded to the planar connection surface of the second portionto foam an interface defining at least one interface edge about theperimeter of the interface between the planar connection surfaces of thefirst portion and the second portion; at least one circuit devicecomprising electrical circuitry, wherein the at least one circuit deviceis encompassed by at least portions of the first portion and the secondportion; and one or more seal portions covering at least the at leastone interface edge of the interface to restrict moisture from ingressinginto the apparatus.
 2. The apparatus of claim 1, wherein the one or moreseal portions comprise deposited material.
 3. The apparatus of claim 1,wherein the one or more seal portions comprise a thickness of at leastabout 1 angstrom.
 4. The apparatus of claim 1, wherein the one or moreseal portions comprise oxide material.
 5. The apparatus of claim 1,wherein the one or more seal portions cover at least a portion of the atleast one side surface of the first portion and the at least one sidesurface of the second portion to restrict moisture from ingressing intothe apparatus.
 6. The apparatus of claim 1, wherein at least one of thefirst portion and the second portion further comprises one or morelayers formed on the substrate thereof terminating at the connectionsurface thereof and defining a portion of the at least one side surfacethereof, wherein the one or more seal portions cover the portion of theat least one side surface defined by the one or more layers to restrictmoisture from ingressing into the apparatus.
 7. The apparatus of claim1, wherein the one or more seal portions at least partially cover thesubstrate surface of the first portion, the substrate surface of thesecond portion, the at least one side surface of the first portion, andthe at least one side surface of the second portion to restrict moisturefrom ingressing into the apparatus.
 8. The apparatus of claim 1, whereinthe connection surface of the first portion defines a larger area thanthe connection surface of the second portion.
 9. The apparatus of claim1, wherein the substrate of the first portion and the substrate of thesecond portion each comprise semiconductor substrates.
 10. The apparatusof claim 1, wherein the at least one circuit device forms a part of animplantable medical device.
 11. The apparatus of claim 1, wherein thefirst portion further comprises one or more layers formed on thesubstrate terminating at the connection surface, wherein the one or morelayers of the first portion comprise a circuit device of the at leastone circuit device.
 12. The apparatus of claim 11, wherein the one ormore layers of the first portion further comprise contact padselectrically coupled to the circuit device and located at the connectionsurface, and wherein second portion further comprises one or more layersformed on the substrate terminating at the connection surface, whereinthe one or more layers of the second portion further comprise a circuitdevice of the at least one circuit device and contact pads electricallycoupled to the circuit device and located at the connection surface,wherein the contact pads of the first portion are electrically coupledto the contact pads of the second portion to electrically couple thecircuit device of the first portion to the circuit device of the secondportion.
 13. The apparatus of claim 1, wherein at least one of the firstportion and the second portion defines a cavity, wherein a circuitdevice of the at least one circuit device is located within the cavity.14. The apparatus of claim 1, wherein the apparatus further comprises:one or more interconnect vias formed in at least one of the firstportion and the second portion and terminating at one or more surfacecontacts at the substrate surface, the connection surface, or the atleast one side surface of at least one of the first and second portions;and at least one electrical interconnect extending from the at least onecircuit device to at least one of the one or more interconnect vias. 15.The apparatus of claim 1, wherein the connection surface of the firstportion is plasma-enhanced bonded to the connection surface of thesecond portion.
 16. A method of providing at least one electricalcircuit apparatus, wherein the method comprises: providing a firstportion, wherein the first portion comprises: a planar connectionsurface, a substrate provided from a wafer, wherein the substratecomprises a substrate surface opposite the planar connection surface,and at least one side surface extending between the substrate surfaceand the planar connection surface, providing a second portion, whereinthe second portion comprises: a planar connection surface, a substrateprovided from a wafer, wherein the substrate comprises a substratesurface opposite the planar connection surface, and at least one sidesurface extending between the substrate surface and the planarconnection surface, providing at least one circuit device comprisingelectrical circuitry; coupling the planar connection surface of thefirst portion to the planar connection surface of the second portion toform an interface defining at least one interface edge about theperimeter of the interface between the planar connection surfaces of thefirst portion and the second portion, wherein the at least one circuitdevice is encompassed by at least portions of the first portion and thesecond portion; and providing one or more seal portions covering atleast the at least one interface edge of the interface to restrictmoisture from ingressing into the apparatus.
 17. The method of claim 16,wherein providing one or more seal portions comprising depositing one ormore seal portions.
 18. The method of claim 16, wherein the one or moreseal portions comprise a thickness of at least about 1 angstrom.
 19. Themethod of claim 16, wherein the one or more seal portions comprise oxidematerial.
 20. The method of claim 16, wherein coupling the planarconnection surface of the first portion to the planar connection surfaceof the second portion comprises oxide bonding the planar connectionsurface of the first portion to the planar connection surface of thesecond portion.
 21. The method of claim 16, wherein coupling the planarconnection surface of the first portion to the planar connection surfaceof the second portion comprises plasma-enhanced bonding the planarconnection surface of the first portion to the planar connection surfaceof the second portion.
 22. The method of claim 16, providing the firstportion comprises providing one or more layers formed on the substratethereof terminating at the connection surface thereof and defining aportion of the at least one side surface thereof, wherein the one ormore seal portions cover at least the portion of the at least one sidesurface defined by the one or more layers to restrict moisture fromingressing into the apparatus to restrict moisture from ingressing intothe apparatus.
 23. The method of claim 22, providing at least onecircuit device comprises forming the at least one circuit within the oneor more layers formed on the substrate of the first portion.
 24. Themethod of claim 16, wherein the one or more seal portions at leastpartially cover each of the substrate surfaces and completely cover theat least one side surfaces of the first portion and the second portionto restrict moisture from ingressing into the apparatus.
 25. The methodof claim 16, wherein the substrate of the first portion and thesubstrate of the second portion each comprise semiconductor substrates.26. The method of claim 16, wherein the at least one circuit deviceforms a part of an implantable medical device.
 27. The method of claim16, wherein at least one of the first portion and the second portiondefines a cavity, wherein a circuit device of the at least one circuitdevice is located within the cavity.
 28. The method of claim 16, whereinthe apparatus further comprises: one or more interconnect vias formed inat least one of the first portion and the second portion and terminatingat one or more surface contacts at the substrate surface, the connectionsurface, or the at least one side surface of at least one of the firstand second portions; and at least one electrical interconnect extendingfrom the at least one circuit device to at least one of the one or moreinterconnect vias.